In recent years, there has been a tremendous push to miniaturize all electrical components, including integrated circuits and other computer chip products. The reduction in the size of ICs has placed a demand on test systems to determine new ways to achieve the tighter spacing needed to test the contact pads of the ICs.
Current processes utilize lithography to produce pad structures of copper and polyimide that have a tight-pitch of 150 μm or less. In these conventional processes, the resulting pads are pliable due to the fact that the pads are routed by copper/polyimide with a flexible polyimide located below the pad. As a result, wire bonding cannot be performed on these pads in a consistent manner.
Recently, a process called Chemical Mechanical Polishing (CMP) was developed to remove material from uneven topography on a wafer surface until a flat (planarized) surface is created. This allows subsequent photolithography to take place with greater accuracy, and enables film layers to be built up with minimal variations in height. CMP combines the chemical removal using a base fluid solution with a mechanical effect provided by abrasive polishing. CMP has particular applicability in the fabrication of copper-based semiconductors, where it is used to define the copper wiring structures.